Desired increases in performance and functionality of integrated circuits have driven designs to very extremely high integration density and extremely small transistor dimensions. While such designs can offer improvements in feasible clock and switching speed and reduced signal propagation time, power requirements, power dissipation constraints and breakdown resistance for increased numbers of transistors in greater proximity and operating at increased clock speeds has required reduction of switching voltage threshold of transistors used in low power designs.
However, reduction of switching threshold of logic transistors scaled to smaller sizes also decreases the off/on resistance ratio of such transistors since reduction of dimensions of the conduction channel tends to increase “on” resistance while lower control voltages tend to increase leakage and decrease “off” resistance. These deviations from ideal switching characteristics tend to increase the power consumption due to leakage currents and compensation thereof as well as compromising noise immunity and susceptibility to switching errors. Therefore, very recent low power integrated circuit designs have included transistors having reduced leakage and operating at increased switching threshold voltages at strategically located points and/or in particular selected paths in the low power circuits to limit the leakage currents which are characteristic of other aggressively scaled low power transistors forming the preponderance of the circuit elements of the integrated circuit. Only one serially connected transistor of NMOS type is suitable for a majority of such circuit paths.
However, such an approach has been accompanied by increased process complexity and higher cost of manufacture. Specifically, to increase the switching threshold and decrease leakage of selected transistors which are of larger size but otherwise process compatible with smaller, low power transistors, it has been necessary to increase the concentration of so-called halo implants surrounding the conduction channel in the transistors. Doing so has required use of an additional mask which introduces additional process complexity and cost while engendering sources of process error (e.g. overlay and/or lithographic errors) and compromising manufacturing yield.